US 7,545,190 B2
Parallel multiplexing duty cycle adjustment circuit with programmable range control
Meei-Ling Chiang, Saratoga, Calif. (US); Sanjeev Maheshwari, San Jose, Calif. (US); and Emerson S. Fang, Fremont, Calif. (US)
Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US)
Filed on May 01, 2007, as Appl. No. 11/742,845.
Prior Publication US 2008/0272814 A1, Nov. 06, 2008
Int. Cl. H03K 3/017 (2006.01)
U.S. Cl. 327—175  [327/172] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a control signal generation circuit configured to generate at least one control signal based, at least in part, on an indicator of a range of a duty cycle adjustment selected from a plurality of ranges of duty cycle adjustment and an indicator of a number of units of duty cycle adjustment selected from a total number of units of duty cycle adjustment spanning the selected range of duty cycle adjustment; and
at least one duty cycle adjustment circuit configured to adjust a duty cycle of a reference clock signal based, at least in part, on the at least one control signal, thereby generating an adjusted version of the reference clock signal.