| US 7,545,176 B2 | ||
| Energy-saving circuit and method using charge equalization across complementary nodes | ||
| Vikas Agarwal, Austin, Tex. (US); Sanjay Dubey, Austin, Tex. (US); Saiful Islam, Austin, Tex. (US); and Gaurav Mittal, Round Rock, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Oct. 25, 2007, as Appl. No. 11/923,714. | ||
| Prior Publication US 2009/0108920 A1, Apr. 30, 2009 | ||
| Int. Cl. H03K 19/0175 (2006.01); H03K 19/094 (2006.01) | ||
| U.S. Cl. 326—86 [326/90; 326/113] | 20 Claims |
| 1. A circuit, comprising:
a pair of complementary dynamic circuit nodes having substantial capacitance, wherein the complementary dynamic nodes can
represent a state expressing a binary value;
a logic input for receiving the binary value and for setting a next state of the complementary dynamic circuit nodes in conformity
therewith;
a change detector for detecting a change in the value as received at the input and generating a pulse at an output of the
change detector in response to the detected value change, wherein the change detector generates the pulse when the next state
of the complementary dynamic circuit nodes differs from a previous state of the complementary circuit nodes, and wherein the
change detector does not generate the pulse when the next state of the complementary dynamic circuit nodes is the same as
the previous state;
a pass gate connected between the complementary dynamic circuit nodes and having a control input coupled to the output of
the change detector for equalizing a voltage between the complementary dynamic circuit nodes during the pulse; and
a pair of driver circuits each having an input coupled to the logic input and an output connected to corresponding one of
the complementary dynamic circuit nodes for setting the next state of the complementary dynamic circuit nodes after the pulse
has terminated.
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