| US 7,545,169 B1 | ||
| FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation | ||
| Wenyi Feng, Sunnyvale, Calif. (US); and Sinan Kaptanoglu, Belmont, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Jul. 15, 2008, as Appl. No. 12/173,225. | ||
| Application 12/173225 is a continuation of application No. 11/855974, filed on Sep. 14, 2007, granted, now 7,408,383. | ||
| Claims priority of provisional application 60/825872, filed on Sep. 15, 2006. | ||
| Int. Cl. H01L 25/00 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—41 [326/47; 326/113] | 6 Claims |
| 1. An interconnect architecture for a programmable logic device comprising:
a plurality of interconnect routing lines;
a plurality of first-level multiplexers each having data inputs and a data output, the data inputs of the first-level multiplexers
connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to at least
two of the plurality of level one multiplexers;
a plurality of second-level multiplexers each having data inputs and a data output, the second-level multiplexers organized
into multiplexer groups; and
a plurality of lookup tables, each lookup table associated with one of the multiplexer groups and having a plurality of lookup
table inputs, each lookup table input coupled to the output of a different one of the second-level multiplexers in the one
of the multiplexer groups with which it is associated;
wherein the data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such
that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer
group.
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