| US 7,545,168 B2 | ||
| Clock tree network in a field programmable gate array | ||
| Arunangshu Kundu, San Jose, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Apr. 18, 2008, as Appl. No. 12/105,524. | ||
| Application 12/105524 is a continuation of application No. 11/387636, filed on Mar. 22, 2006, granted, now 7,375,553. | ||
| Application 11/387636 is a continuation of application No. 10/916926, filed on Aug. 11, 2004, granted, now 7,049,846, filed on May 23, 2006. | ||
| Application 10/916926 is a continuation of application No. 10/448258, filed on May 28, 2003, granted, now 6,825,690, filed on Nov. 30, 2004. | ||
| Prior Publication US 2008/0191740 A1, Aug. 14, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—41 [326/40; 326/47; 326/101; 327/141; 327/144; 327/150; 327/156] | 9 Claims |
| 1. A clock tree distribution network for a field programmable gate array (FPGA) comprising:
a clock-source selector providing a root signal selected from at least one of an external clock signal, an internal clock
signal and at least one phase lock loop cell output signal;
an array of programmable logic coupled to the clock-source selector, the logic array having a plurality of combinatorial logic
modules having inputs and a plurality of sequential logic modules having clock inputs;
a hardwired clock network that selects a signal from at least one of the root signal, a local signal from the array of programmable
logic, a positive power supply signal, and a ground signal and routes the selected signal to the clock inputs of the plurality
of sequential logic modules in the array of programmable logic; and
a routed clock network that selects a signal from at least one of the root signal, a local signal from the array of programmable
logic, a positive power supply signal, and a ground signal and routes the selected signal through at least one programmable
element to at least one of the clock inputs of the plurality of sequential logic modules in the array of programmable logic.
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