| US 7,545,166 B2 | ||
| Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers | ||
| Donald Y. Yu, Fremont, Calif. (US); and Wei-Min Kuo, San Jose, Calif. (US) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Apr. 25, 2008, as Appl. No. 12/109,487. | ||
| Application 12/109487 is a continuation of application No. 11/548199, filed on Oct. 10, 2006, granted, now 7,378,867. | ||
| Application 11/548199 is a continuation of application No. 11/123734, filed on May 05, 2005, granted, now 7,119,573, filed on Oct. 10, 2006. | ||
| Application 11/123734 is a continuation of application No. 10/163096, filed on Jun. 04, 2002, granted, now 6,891,394, filed on May 10, 2005. | ||
| Prior Publication US 2008/0197905 A1, Aug. 21, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 19/173 (2006.01) | ||
| U.S. Cl. 326—38 [326/47] | 6 Claims |
| 1. A field programmable gate array comprising:
a low voltage signaling driver circuit having a first input line, a second input line, a first output line, and a second output
line comprising:
a first output buffer having an input and an output connected to the first output line;
a second output buffer having an input and an output connected to the second output line;
a delay circuit responsively connected to said first input line;
an inverter responsively connected to said first input line;
a first multiplexer having a first input connected to an output of said delay circuit, a second input connected to said first
input line, a selector, and an output connected to the input of said first output buffer; and
a second multiplexer having a first input connected to an output of said inverter, a second input connected to said second
input line, a selector, and an output connected to the input of said second output buffer;
and
programmable elements coupled to the selectors of and providing signals to control the first multiplexer and the second multiplexer.
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