US 7,545,027 B2
Wafer level package having redistribution interconnection layer and method of forming the same
Hyun-Soo Chung, Hwaseong-si (Korea, Republic of); In-Young Lee, Yongin-si (Korea, Republic of); Dong-Hyeon Jang, Suwon-si (Korea, Republic of); Myeong-Soon Park, Suwon-si (Korea, Republic of); and Dong-Ho Lee, Seongnam-si (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (Korea, Republic of)
Filed on Jun. 08, 2006, as Appl. No. 11/448,772.
Claims priority of application No. 10-2005-0110123 (KR), filed on Nov. 17, 2005.
Prior Publication US 2007/0108573 A1, May 17, 2007
Int. Cl. H01L 23/02 (2006.01)
U.S. Cl. 257—678  [257/701; 438/106; 438/121; 438/125] 22 Claims
OG exemplary drawing
 
1. A wafer level package, comprising:
a semiconductor substrate supporting an electrode pad;
a first insulating layer provided on the semiconductor substrate, the first insulating layer having a first opening through which the electrode pad is exposed;
a seed metal layer provided on the electrode pad and the first insulating layer;
a redistribution interconnection metal layer provided on a portion of a surface of the seed metal layer so that an edge portion of the surface of the seed metal layer is exposed;
a second insulating layer provided on the exposed edge portion of the surface of the seed metal layer and the redistribution interconnection metal layer, the second insulating layer having a second opening through which a portion of the redistribution interconnection metal layer is exposed, the exposed portion of the redistribution interconnection metal layer being spaced apart from the electrode pad; and
an external connection electrode provided on the exposed portion of the redistribution interconnection metal layer,
wherein the seed metal layer extends beyond a side of the redistribution interconnection metal layer, and the second insulating layer is provided on the redistribution interconnection metal layer and the extended portion of the seed metal layer.