| US 7,544,999 B2 | ||
| SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate | ||
| Andy C. Wei, Radebeul/Dresden (Germany); Derick J. Wristers, Bee Caves, Tex. (US); and Mark B. Fuselier, Austin, Tex. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on Mar. 04, 2005, as Appl. No. 11/72,661. | ||
| Application 11/072661 is a division of application No. 10/162299, filed on Jun. 04, 2002, granted, now 6,884,702. | ||
| Prior Publication US 2005/0151133 A1, Jul. 14, 2005 | ||
| Int. Cl. H01L 27/12 (2006.01) | ||
| U.S. Cl. 257—347 [257/349; 257/396; 257/E27.112] | 13 Claims |
| 1. A semiconductor device, comprising:
a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer formed above the bulk
substrate, and an active layer formed above the buried insulation layer; and
a plurality of dielectric regions formed in said bulk substrate, said dielectric regions being self-aligned with respect to
said gate electrode, said dielectric regions having a dielectric constant that is less than a dielectric constant of said
bulk substrate.
|