| US 7,544,976 B2 | ||
| Semiconductor heterostructure | ||
| Cécile Aulnette, Grenoble (France); and Christophe Figuet, Crolles (France) | ||
| Assigned to S.O.I.Tec Silicon on Insulator Technologies, Bernin (France) | ||
| Filed on Feb. 08, 2007, as Appl. No. 11/672,663. | ||
| Claims priority of application No. 06291955 (EP), filed on Dec. 15, 2006. | ||
| Prior Publication US 2008/0142844 A1, Jun. 19, 2008 | ||
| Int. Cl. H01L 31/00 (2006.01) | ||
| U.S. Cl. 257—190 [257/E29.193; 257/E21.086] | 19 Claims |
| 1. A semiconductor heterostructure comprising:
a support substrate with a first in-plane lattice parameter,
a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter,
and
a multi-layer stack of ungraded layers formed on the buffer structure,
wherein the ungraded layers are strained layers comprising at least one strained smoothing layer of a semiconductor material
having in a relaxed state a third in-plane lattice parameter which has a value between that of the first and the second lattice
parameters, and
wherein the total thickness of the smoothing layer and all further layers that are not lattice matched with the buffer structure
are less than a critical thickness to prevent nucleation of dislocations or other defects.
|