| US 7,544,602 B2 | ||
| Method and structure for ultra narrow crack stop for multilevel semiconductor device | ||
| Lawrence A. Clevenger, LaGrangeville, N.Y. (US); Matthew E. Colburn, Hopewell Junction, N.Y. (US); William F. Landers, Wappingers Falls, N.Y. (US); and Wai-Kin Li, Beacon, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Mar. 29, 2007, as Appl. No. 11/693,033. | ||
| Prior Publication US 2008/0237868 A1, Oct. 02, 2008 | ||
| Int. Cl. H01L 23/522 (2006.01) | ||
| U.S. Cl. 438—619 [438/638; 257/E21.581; 257/E23.17] | 1 Claim |
| 1. A method of forming a structure, comprising:
forming a connection via in a level of dielectric material;
forming a crack stop feature via in the level of dielectric material;
filling the connection via with metallization while blocking off the crack stop feature via to form a crack stop structure
in the level of dielectric material; and
forming an air gap feature in the first level of dielectric by forming an air gap via and blocking the air gap via during
the filling, wherein
the crack stop structure extends through at least a second level of dielectric by forming a via through at least the second
level of dielectric and blocking the via while performing a metallization process which forms a higher level connection feature,
the blocking comprises an chemical vapor deposition process to pinch off openings of the crack stop feature via,
the crack stop feature via and a portion of the connection via are formed in a single etching step,
the crack stop structure is formed outside an active area, and
the crack stop structure has a width of about less than 1 um.
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