| US 7,544,586 B2 | ||
| Method of fabricating chips and an associated support | ||
| Bruno Ghyselen, Seyssinet-Pariset (France); and Olivier Rayssac, Grenoble (France) | ||
| Assigned to S.O.I. Tec Silicon on Insulator Technologies, Bernin (France) | ||
| Filed on May 23, 2005, as Appl. No. 11/136,252. | ||
| Prior Publication US 2005/0236700 A1, Oct. 27, 2005 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 438—460 [438/462] | 30 Claims |
| 1. A method of fabricating a plurality of chips, each chip comprising at least one circuit, which method comprises the following
steps in succession:
creating chips on a layer of semiconductor material that is integral with a substrate;
forming a weakening pattern corresponding to a predetermined cutting pattern on a support;
transferring a layer of semiconductor material that contains the chips from the substrate to the support; and
forming individual chips by cutting the chip-containing layer in accordance with the predetermined cutting pattern.
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