| US 7,544,575 B2 | ||
| Dual metal silicide scheme using a dual spacer process | ||
| Olubunmi O. Adetutu, Austin, Tex. (US); Dharmesh Jawarani, Round Rock, Tex. (US); and Randy W. Cotton, Pflugerville, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Jan. 19, 2006, as Appl. No. 11/337,036. | ||
| Prior Publication US 2007/0166937 A1, Jul. 19, 2007 | ||
| Int. Cl. H01L 21/336 (2006.01) | ||
| U.S. Cl. 438—299 [438/592; 438/664; 257/E21.438] | 20 Claims |
| 19. A method for fabricating silicide regions using two silicide formation processes, comprising:
forming first silicide regions in a polysilicon gate and active source/drain regions;
forming sidewall spacers adjacent the polysilicon gate to partially cover at least part of the first silicide regions in the
active source/drain regions; and then
forming second silicide regions in the polysilicon gate and any exposed surface of the active source/drain regions not covered
by the sidewall spacers by using the sidewall spacers to effectively separate the second silicide regions in the active source/drain
regions further from a channel region than the first silicide regions, thereby reducing encroachment of the second silicide
regions.
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