| US 7,544,570 B2 | ||
| Vertical-type metal insulator semiconductor field effect transistor device, and production method for manufacturing such transistor device | ||
| Kinya Ohtani, Kanagawa (Japan) | ||
| Assigned to NEC Electronics Corporation, Kawasaki, Kanagawa (Japan) | ||
| Filed on Oct. 03, 2006, as Appl. No. 11/541,535. | ||
| Application 11/541535 is a division of application No. 10/998943, filed on Nov. 30, 2004, granted, now 7,135,739. | ||
| Claims priority of application No. 2003-425974 (JP), filed on Dec. 22, 2003. | ||
| Prior Publication US 2007/0023826 A1, Feb. 01, 2007 | ||
| Int. Cl. H01L 21/331 (2006.01) | ||
| U.S. Cl. 438—268 [438/212; 257/329; 257/328; 257/E21.383] | 7 Claims |
| 1. A production method for manufacturing a vertical-type metal insulator field effect transistor device, comprising:
preparing a first conductivity type drain region layer;
forming a plurality of trenches at a given pitch in the first conductivity type drain region layer;
stuffing said trenches with an insulating material to thereby producing buried-insulator regions;
forming a gate insulating layer on said first conductivity type drain region;
implanting second conductivity type impurities in said first conductivity type drain region layer to thereby produce a plurality
of second conductivity type base regions in said first conductivity type drain region layer such that each of the second conductivity
type base regions is positioned between two adjacent buried-insulator regions;
forming a gate electrode layer on said gate insulating layer;
patterning said gate electrode layer such that a portion of said gate electrode layer is defined as a span portion which bridges
a space between two adjacent second conductivity type base regions;
implanting first conductivity type impurities in said second conductivity type base regions to thereby produce a first conductivity
type source region in each of said second conductivity type base regions; and
patterning said gate insulating layer such that a portion of said gate insulating layer is defined as a span portion which
bridges a space between two adjacent second conductivity type base regions.
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