| US 7,544,552 B2 | ||
| Method for manufacturing junction semiconductor device | ||
| Ken-ichi Nonaka, Wako (Japan); Hideki Hashimoto, Wako (Japan); Seiichi Yokoyama, Wako (Japan); Kensuke Iwanaga, Wako (Japan); Yoshimitsu Saito, Wako (Japan); Hiroaki Iwakuro, Hanno (Japan); Masaaki Shimizu, Hanno (Japan); Yusuke Fukuda, Hanno (Japan); Koichi Nishikawa, Hanno (Japan); and Yusuke Maeyama, Hanno (Japan) | ||
| Assigned to Honda Motor Co., Ltd., Tokyo (Japan); and Shindengen Electric Manufacturing Co., Ltd., Tokyo (Japan) | ||
| Filed on Mar. 23, 2006, as Appl. No. 11/386,661. | ||
| Claims priority of application No. P2005-084671 (JP), filed on Mar. 23, 2005. | ||
| Prior Publication US 2006/0216879 A1, Sep. 28, 2006 | ||
| Int. Cl. H01L 21/337 (2006.01); H01L 29/772 (2006.01); H01L 21/339 (2006.01); H01L 21/338 (2006.01); H01L 29/768 (2006.01); H01L 29/78 (2006.01) | ||
| U.S. Cl. 438—186 [438/146; 438/175; 438/188; 257/213; 257/288; 257/347; 257/352; 257/E29.233; 257/E29.27; 257/E29.243] | 21 Claims |

| 1. A method for manufacturing a junction semiconductor device, comprising:
forming a first high-resistance layer on one surface of a semiconductor substrate of a first conductive type;
forming a channel-doped layer on said first high-resistance layer;
forming a second high-resistance layer on said channel-doped layer;
forming a low-resistance layer of a first conductive type that acts as a source region directly on an upper surface of said
second high-resistance layer;
performing etching through said low-resistance layer and partial etching through said second high-resistance layer until a
midway depth thereof so that a partially etched-out portion of the second high-resistenace layer has a bottom lying between
a lower surface of the source region and an upper surface of the channel-doped layer;
forming a gate region below the partially etched-out portion of the second high-resistance layer;
forming a protective film on a surface of a region between said gate region and said source region;
joining a source electrode on said low-resistance layer; a gate electrode on said gate region, and a drain electrode on the
other surface of said semiconductor substrate; and
forming an upper layer electrode above the source electrode and the gate electrode,
wherein the step of forming the protective film includes forming the protective film along a bottom of the recessed-shaped
etched portion, on which the gate electrode is subsequently disposed.
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