| US 7,544,548 B2 | ||
| Trench liner for DSO integration | ||
| Mariam G. Sadaka, Austin, Tex. (US); Ted R. White, Austin, Tex. (US); and Bich-Yen Nguyen, Austin, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on May 31, 2006, as Appl. No. 11/443,628. | ||
| Prior Publication US 2007/0281436 A1, Dec. 06, 2007 | ||
| Int. Cl. H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—154 [438/198; 438/222; 257/E21.642] | 22 Claims |

| 1. A method for fabricating a dual substrate semiconductor structure, comprising:
forming a first semiconductor layer having a first crystal orientation;
forming a second semiconductor layer over at least part of the first semiconductor layer, wherein the second semiconductor
layer is electrically isolated from the first semiconductor layer by a buried oxide layer and has a second crystal orientation
that is different from the first crystal orientation;
forming a first trench by selectively removing a portion of the second semiconductor layer in a first predetermined region;
depositing a first trench liner in the first trench;
depositing a first oxide layer over the first trench liner;
polishing the first trench liner and first oxide layer down to an underlying polish stop layer;
forming a second trench to expose the first semiconductor layer without exposing the second semiconductor layer by selectively
removing a portion of the first oxide layer, first trench liner, and buried oxide layer in a second predetermined region contained
within the first predetermined region;
depositing a second trench liner in the second trench;
anisotropically etching the second trench liner to expose the first semiconductor layer while leaving a portion of the second
trench liner on vertical sidewalls of the second trench; and
filling at least part of the second trench with a third semiconductor layer that is electrically isolated from the second
semiconductor layer and that has a third crystal orientation that is the same as the first crystal orientation by epitaxially
growing silicon on an exposed surface of the first semiconductor layer.
|