| US 7,544,542 B2 | ||
| Reduction of damage to thermal interface material due to asymmetrical load | ||
| Seah Sun Too, San Jose, Calif. (US); Raj N. Master, San Jose, Calif. (US); Jacquana Diep, San Jose, Calif. (US); and Mohammad Khan, Santa Clara, Calif. (US) | ||
| Assigned to Advanced Micro Devices, Inc., Sunnyvale, Calif. (US) | ||
| Filed on Aug. 07, 2006, as Appl. No. 11/462,993. | ||
| Prior Publication US 2008/0124841 A1, May 29, 2008 | ||
| Int. Cl. H01L 21/44 (2006.01) | ||
| U.S. Cl. 438—125 [257/E23.087; 257/E23.09; 257/E23.092; 257/E25.013] | 18 Claims |
| 1. A method of packaging an integrated circuit, comprising:
coupling an integrated circuit to a substrate, the substrate including a plurality of conductor structures therein;
placing a thermal interface film on the integrated circuit, the thermal interface film having a polymer matrix and a plurality
of metallic particles dispersed therein;
mixing an adhesive with a plurality of particles so as to form a bed of particles being retained by the adhesive wherein the
particles are not adapted to be physically bonded to one another after being mixed with the adhesive; and
coupling a lid to the substrate with the adhesive, at least a portion of the plurality of particles in the adhesive opposing
compressive force from the lid to restrict rotation of the lid relative to the substrate and constrain spatial separation
of the metallic particles.
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