US 7,544,058 B2
	Method for high-temperature annealing a multilayer wafer
Christophe Maleville, La Terrasse (France); Walter Schwarzenbach, Saint Nazaire les Eymes (France); and Vivien Renauld, Pontcharra (France)
Assigned to S.O.I.Tec Silicon on Insulator Technologies, Bernin (France)
Filed on Jul. 13, 2007, as Appl. No. 11/777,728.
Application 11/777728 is a continuation of application No. PCT/IB2005/000483, filed on Feb. 03, 2005.
Prior Publication US 2007/0298363 A1, Dec. 27, 2007
Int. Cl. F27B 9/12 (2006.01)

U.S. Cl. 432—18  [432/5; 432/12]

13 Claims

1. A method for annealing a multilayer silicon-on-insulator wafer which comprises subjecting the wafer to a high temperature treatment that includes at least a temperature ramp-up between a boat-in temperature and a process temperature of at least 800° C. ; at least a processing phase conducted at or above the process temperature; and a temperature ramp-down from the processing phase to a boat-out temperature, wherein the boat-in temperature is between 50 and 350 degrees Centigrade lower than the boat-out temperature to reduce or avoid tearing-off defects on the wafer and to reduce particle contaminants on the wafer, as well as to reduce or avoid degrading wafer Dit compared to an annealing method where the boat-in and boat-out temperatures are closer in temperature.