| US 7,381,986 B2 | ||
| Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer | ||
| Brion L. Keller, Binghamton, N.Y. (US); Bernd K. F. Koenermann, San Jose, Calif. (US); David E. Lackey, Jericho, Vt. (US); and Donald L. Wheater, Hinesburg, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jun. 28, 2006, as Appl. No. 11/477,963. | ||
| Application 11/477963 is a division of application No. 10/248380, filed on Jan. 15, 2003, abandoned. | ||
| Prior Publication US 2006/0284174 A1, Dec. 21, 2006 | ||
| Int. Cl. H01L 23/58 (2006.01) | ||
| U.S. Cl. 257—48 | 8 Claims |
| 1. A semiconductor wafer, comprising:
a semiconductor substrate;
a plurality of integrated circuit chips formed in said substrate;
said plurality of integrated circuit chips being formed in said semiconductor substrate to create a plurality of rows separated
one row from another by a respective row kerf there between and a plurality of columns separated one column row from another
by a respective column kerf;
first, second, third and fourth tester interface circuits formed on said substrate;
said first and said second tester interface circuit being coupled to each of said integrated circuit chips formed in said
semiconductor substrate through first and second respective wiring paths located in said row kerfs;
said third and said fourth tester interface circuit being coupled to each of said integrated circuit chips formed in said
semiconductor substrate through third and fourth respective wiring paths located in said column kerfs; and
each of said wiring paths having a plurality of distinct stimulus busses in each respective kerf area for providing each integrated
circuit chip coupled thereto with power, parallel serial scan data, clock, control, chip enable data enable signals; and an
output means for obtaining the response of said integrated circuit chips to such inputs.
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