| US 7,543,265 B1 | ||
| Method for early logic mapping during FPGA synthesis | ||
| Gregg William Baeckler, San Jose, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Apr. 26, 2006, as Appl. No. 11/412,322. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—18 [716/17] | 10 Claims |
| 2. A method of synthesizing a logic design for technology mapping on a target device, said method comprising:
performing a high level synthesis of the logic design to generate a net list;
performing a multilevel synthesis on the net list to generate a gate implementation of the net list; and
performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target
device,
wherein, during the performance of the high level synthesis of the logic design into the net list, technology mapping is further
performed on a selected portion of the logic design to improve the predictability of the power, area and/or frequency of the
logic design without substantially degrading the performance of the power, area and frequency of the logic design, wherein,
during the technology mapping performed during the high level synthesis, each gate is sequentially reviewed in the net list,
and each gate is classified as either soft, hard, or firm.
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