| US 7,543,260 B2 | ||
| Design supporting system of semiconductor integrated circuit, method of designing semiconductor integrated circuit, and computer readable medium for supporting design of semiconductor integrated circuit | ||
| Toshiaki Ueda, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jun. 28, 2006, as Appl. No. 11/476,181. | ||
| Claims priority of application No. 2005-188379 (JP), filed on Jun. 28, 2005. | ||
| Prior Publication US 2007/0101307 A1, May 03, 2007 | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—10 [716/5] | 12 Claims |
| 1. A design supporting system of a semiconductor integrated circuit, comprising:
a unit that converts a defective circuit pattern into computer detectable information when a layout of chip of the semiconductor
integrated circuit is determined, and corrects the defective circuit pattern of the layout of the chip based on the computer
detectable information;
a layout designing unit that decides the layout of the chip by defining a plurality of areas in the chip and automatically
placing/routing wirings and vias;
a data storing equipment that stores the computer detectable information of the defective circuit pattern;
a manufacturability analyzing unit that reads the computer detectable information of the defective circuit pattern, verifies
the computer detectable information of the defective circuit pattern and the layout of the chip decided by the layout designing
unit, and analyzes a manufacturability of the layout of the chip, wherein
the computer detectable information of the defective circuit pattern and the layout of the chip decided by the layout designing
unit can be verified, and
the manufacturability analyzing unit analyzes the manufacturability of the layout of the chip based on an occurring frequency
of the defective circuit pattern which is calculated in each area of the plurality of areas in the chip.
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