| US 7,543,258 B2 | ||
| Clock design apparatus and clock design method | ||
| Takeshi Kitahara, Kawasaki (Japan); and Yoshiki Tsukiboshi, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 11, 2006, as Appl. No. 11/402,525. | ||
| Claims priority of application No. P2005-116208 (JP), filed on Apr. 13, 2005. | ||
| Prior Publication US 2006/0253821 A1, Nov. 09, 2006 | ||
| Int. Cl. G06F 17/50 (2006.01); G06F 9/45 (2006.01) | ||
| U.S. Cl. 716—6 [716/1; 716/5; 716/18] | 19 Claims |
| 1. A clock design apparatus comprising:
a delay time adjusting section configured to adjust signal delay time of signal propagation paths on a semiconductor integrated
circuit to be designed;
a prohibition specifying section configured to provide circuit specifications which identify a part of the signal propagation
paths as a circuit prevented from being changed; and
a clock tree synthesis section configured to perform a clock tree synthesis (CTS) process to synthesize a clock tree of the
semiconductor integrated circuit in accordance with the circuit specifications made by the prohibition specifying section,
wherein delay times associated with fixed delay information are obtained;
wherein the delay adjusting section is configured to specify delay as a function of the delay times:wherein the semiconductor integrated circuit comprises a first logical block, and a second logical block, wherein an operating
frequency of the second logical block and a voltage supplied to the second logical block are variable;wherein an operating frequency of the first logical block and a voltage supplied to the first logical block are predetermined
fixed values: andwherein clock delay adjustments that are independent of changes to apparatus supply voltages may be obtained as a function
of the specified delay.
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