	US 7,543,203 B2
	LSSD-compatible edge-triggered shift register latch
Gerry Ashton, Castleton, Vt. (US); Kevin A. Duncan, Milton, Vt. (US); Terry D. Keim, Williston, Vt. (US); Toshiharu Saitoh, South Burlington, Vt. (US); and Tad J. Wilder, South Hero, Vt. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Feb. 27, 2004, as Appl. No. 10/708,382.
Prior Publication US 2005/0204244 A1, Sep. 15, 2005
Int. Cl. G01R 31/28 (2006.01)

U.S. Cl. 714—726

20 Claims

1. An integrated circuit, comprising:

a) a first shift register latch responsive to a first clock signal;

b) at least one second shift register latch responsive to said first clock signal, wherein said first clock signal at said at least one second shift register latch has a delay relative to said first clock signal at said first shift register, said at least one second shift register latch comprising:

i) a first latch;

ii) a second latch in electrical communication with said first latch;

iii) an input for receiving said first clock signal; and

iv) a delay-compensation circuit connected between said input and said first latch, said delay-compensation circuit configured to generate a second clock signal as a function of said first clock signal so as to compensate for said delay in said first clock signal.