| US 7,543,172 B2 | ||
| Strobe masking in a signaling system having multiple clock domains | ||
| Jade M. Kizer, Durham, N.C. (US); Sivakumar Doraiswamy, San Jose, Calif. (US); and Benedict Lau, San Jose, Calif. (US) | ||
| Assigned to Rambus Inc., Los Altos, Calif. (US) | ||
| Filed on Dec. 21, 2004, as Appl. No. 11/19,432. | ||
| Prior Publication US 2006/0136769 A1, Jun. 22, 2006 | ||
| Int. Cl. G06F 1/12 (2006.01) | ||
| U.S. Cl. 713—401 [713/400; 713/500; 713/600] | 44 Claims |
| 1. A memory controller comprising:
a delay circuit that couples to an enable signal and a clock signal, the enable signal and clock signal being clocked at a
first phase;
a selection circuit that controls an adjustable delay of the delay circuit;
a latch circuit that latches a delayed enable signal from the delay circuit in response to a strobe signal being clocked at
a second phase; and
a mask circuit to generate a masked strobe signal that lacks a transition of the strobe signal that occurs prior to latching
the delayed enable signal in the latch circuit.
|