a processor;

a memory management module comprising a plurality of instructions executable on the processor;

an input/output memory management unit (IOMMU) configured to implement address translation and memory protection for memory operations sourced by one or more input/output (I/O) devices; and

a memory subsystem comprising a memory controller and a memory coupled to the memory controller;

wherein the memory stores a command queue during use, and wherein the memory management module is configured to write one or more control commands to the command queue, and wherein the IOMMU is configured to read the control commands from the command queue and execute the control commands, and wherein the control commands comprise invalidate commands defined to invalidate cached translation data in the IOMMU, wherein the cached translation data is used by the IOMMU to perform the address translation and memory protection for memory requests sourced by the I/O devices.