| US 7,543,091 B2 | ||
| Self-organized parallel processing system | ||
| Yoshiyuki Hamaoka, Austin, Tex. (US); Kazuko Ishibashi, Austin, Tex. (US); and Hiroo Hayashi, Round Rock, Tex. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 22, 2004, as Appl. No. 10/946,790. | ||
| Prior Publication US 2006/0075265 A1, Apr. 06, 2006 | ||
| Int. Cl. G06F 13/00 (2006.01); G06F 9/00 (2006.01); G06F 15/177 (2006.01); G06F 1/24 (2006.01) | ||
| U.S. Cl. 710—104 [713/1; 713/100] | 48 Claims |
| 1. A method implemented in a system having a plurality of processors embedded in a general purpose processor, wherein each
of the processors is implemented in an integrated circuit and has a corresponding configuration object installed thereon,
and wherein each configuration object is composed of programming that is installed on the corresponding processor to enable
the processor to assist in the execution of a user application, the method comprising:
(a) evaluating performance of each configuration object of a current set of the configuration objects installed on the plurality
of processors;
(b) selecting a preferred set of configuration objects based on the evaluated performance of the configuration objects in
the current set; and
(c) replacing one or more of the configuration objects in the current set to conform the current set to the preferred set,
wherein replacing one or more of the configuration objects in the current set comprises replacing a first configuration object
having a lower data processing efficiency with a second configuration object having a higher data processing efficiency, the
method further comprising reducing a clock rate of the processor on which the second configuration object is installed in
response to replacing the first configuration object with the second configuration object.
|