| US 7,542,857 B2 | ||
| Technique for determining performance characteristics of electronic devices and systems | ||
| Haw-Jyh Liaw, Fremont, Calif. (US); Xiangchao Yuan, Palo Alto, Calif. (US); and Mark A. Horowitz, Menlo Park, Calif. (US) | ||
| Assigned to Rambus Inc., Los Altos, Calif. (US) | ||
| Filed on Feb. 16, 2006, as Appl. No. 11/354,964. | ||
| Application 11/354964 is a division of application No. 10/954489, filed on Oct. 01, 2004, granted, now 7,006,932. | ||
| Application 10/954489 is a continuation of application No. 09/799516, filed on Mar. 07, 2001, granted, now 6,920,402. | ||
| Prior Publication US 2006/0136153 A1, Jun. 22, 2006 | ||
| Int. Cl. G01R 15/00 (2006.01); G06F 19/00 (2006.01) | ||
| U.S. Cl. 702—57 [702/64; 702/79; 702/117; 324/532] | 12 Claims |
| 1. A method for determining worst case bit sequences, the method comprising the steps of:
acquiring a first representation of a first response on a first signal line resulting from a first signal transmitted on the
first signal line;
acquiring a second representation of a second response on the first signal line resulting from at least one second signal
transmitted on at least one second signal line, the at least one second signal line being substantially adjacent to the first
signal line; and
generating worst case bit sequences based upon the first representation of the first response and the second representation
of the second response for transmission on the first signal line and the at least one second signal line for use in determining
performance characteristics associated with at least the first signal line;
wherein generating worst case bit sequences comprises generating worst case timing margin bit sequences and worst case voltage
margin bit sequences for transmission on the first signal line and the at least one second signal line, wherein generating
worst case timing margin bit sequences for transmission on the first signal line comprises determining a polarity of the first
response at data-cell boundaries of the first response, wherein if the polarity at a data-cell boundary is positive, then
an associated bit in a first worst case timing margin bit sequence for transmission on the first signal line is assigned a
logic one value, and wherein if the polarity at a data-cell boundary is negative, then an associated bit in the first worst
case timing margin bit sequence for transmission on the first signal line is assigned a logic zero value.
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