| US 7,542,523 B2 | ||
| Pipeline architecture for multi-slot wireless link processing | ||
| Baoguo Yang, Iselin, N.J. (US); Li Fung Chang, Holmdel, N.J. (US); and Zhijun Gong, Iselin, N.J. (US) | ||
| Assigned to Broadcom Corporation, Irvine, Calif. (US) | ||
| Filed on Nov. 02, 2005, as Appl. No. 11/265,021. | ||
| Application 11/265021 is a continuation of application No. 10/731858, filed on Dec. 09, 2003, granted, now 7,027,539. | ||
| Claims priority of provisional application 60/431940, filed on Dec. 09, 2002. | ||
| Claims priority of provisional application 60/478922, filed on Jun. 16, 2003. | ||
| Prior Publication US 2006/0050816 A1, Mar. 09, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H03K 9/00 (2006.01) | ||
| U.S. Cl. 375—316 [375/229; 375/350; 375/346; 455/307; 708/300] | 32 Claims |
| 1. A method for processing baseband signals corresponding to N slots of a Radio Frequency (RF) time divided frame by an RF
receiver, the method comprising:
for a first slot of the N slots:
pre-equalization processing a first slot baseband signal; and
equalizing the first slot baseband signal after pre-equalization processing the first slot baseband signal;
for each of a second through Nth slots:
pre-equalization processing a current slot baseband signal while equalizing a prior slot baseband signal;
equalizing the current slot baseband signal; and
post-equalization processing the prior slot baseband signal while equalizing the current slot baseband signal; and
post-equalization processing an Nth slot baseband signal.
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