	US 7,542,521 B2
	Direct-conversion frequency mixer
Byoung Gun Choi, Daejeon (Korea, Republic of); Seok Bong Hyun, Daejeon (Korea, Republic of); Geum Young Tak, Seoul (Korea, Republic of); Hee Tae Lee, Daejeon (Korea, Republic of); Seong-Su Park, Daejeon (Korea, Republic of); and Chul Soon Park, Daejeon (Korea, Republic of)
Assigned to Electronics and Telecommunications Research Institute, Daejeon (Korea, Republic of)
Filed on Sep. 14, 2005, as Appl. No. 11/226,045.
Claims priority of application No. 10-2004-0084718 (KR), filed on Oct. 22, 2004.
Prior Publication US 2006/0088122 A1, Apr. 27, 2006
Int. Cl. H03K 9/00 (2006.01)

U.S. Cl. 375—316 [375/235; 375/261; 375/280; 375/282; 375/283; 375/331]

13 Claims

1. A direct-conversion frequency mixer comprising:

a 1^stfrequency mixing unit (FMU) for direct-converting a single phase radio frequency (SPRF) signal into an in-phase baseband signal by using quadrature local oscillation (QLO) signals having respective phases of 0 degrees and 180 degrees such that the 1^stFMU comprises 1^st, 2^nd, 3^rd, and 4^thtransistors,

the 1^stand 4^thtransistors of the 1^stFMU having gates coupled to 0 and 180 degree phase QLO signals, respectively,

the 2^ndand 3^rdtransistors of the 1^stFMU having gates coupled to the SPRF signal, wherein

the 1^stand 2^ndtransistors of the 1^stFMU having drains commonly coupled together and coupled to a bias voltage (VDD) such that a common drain node of the 1^stand 2^ndtransistors of the 1^stFMU for outputting a positive in-phase baseband (IP+BB) signal,

the 3^rdand 4^thtransistors of the 1^stFMU having drains commonly coupled together and coupled to the VDD such that a common drain node of the 3^rdand 4^thtransistors of the 1^stFMU for outputting a negative in-phase baseband (IP−BB) signal; and

a 2^ndfrequency mixing unit (FMU) for direct-converting SPRF signal into a quadrature-phase baseband signal by using QLO signals having respective phases of 90 degrees and 270 degrees such that the 2^ndFMU comprises four transistors,

the 1^stand 4^thtransistors of the 2^ndFMU having gates coupled to 90 and 270 degree phase QLO signals, respectively,

the 2^ndand 3^rdtransistors of the 2^ndFMU having gates coupled to the SPRF signal, wherein

the 1^stand 2^ndtransistors of the 2^ndFMU having drains commonly coupled together and coupled to the VDD such that a common drain node of the 1^stand 2^ndtransistors of the 2^ndFMU for outputting a positive quadrature phase baseband (QP+BB) signal, and

the 3^rdand 4^thtransistors of the 2^ndFMU having drains commonly coupled together and coupled to the VDD such that a common drain node of the 3^rdand 4^thtransistors of the 2^ndFMU for outputting a negative quadrature phase baseband (QP−BB) signal;

wherein the 1^stFMU and the 2^ndFMU are driven by the VDD supplied from a single voltage source and wherein the 1^stFMU and the 2^ndFMU are parallel to each other and not stacked relative to the VDD.