| US 7,542,372 B2 | ||
| Circuit and methods for eliminating skew between signals in semiconductor integrated circuit | ||
| Seung-Jun Bae, Seo-gu (Korea, Republic of); Kwang-Il Park, Yongin-si (Korea, Republic of); and Seong-Jin Jang, Seongnam-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Jun. 29, 2007, as Appl. No. 11/770,766. | ||
| Claims priority of application No. 10-2006-0060285 (KR), filed on Jun. 30, 2006. | ||
| Prior Publication US 2008/0123454 A1, May 29, 2008 | ||
| Int. Cl. G11C 8/00 (2006.01) | ||
| U.S. Cl. 365—233.1 [365/233.11; 365/222; 365/194] | 9 Claims |
| 1. A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device
and a memory controller, the circuit comprising:
an edge information storage unit which stores edge information output from the semiconductor memory device;
a pseudo data pattern generating unit which outputs pseudo data including a pattern corresponding to actually transmitted
data;
a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from
the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a
corresponding detection result; and
a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase
detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor
memory device.
|