| US 7,542,368 B2 | ||
| Semiconductor memory device | ||
| Satoshi Ishikura, Osaka (Japan); Hironori Akamatsu, Osaka (Japan); Kazuo Itoh, Osaka (Japan); and Yoshinobu Yamagami, Kyoto (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Dec. 06, 2006, as Appl. No. 11/634,110. | ||
| Claims priority of application No. 2005-353947 (JP), filed on Dec. 07, 2005. | ||
| Prior Publication US 2007/0133326 A1, Jun. 14, 2007 | ||
| Int. Cl. G11C 5/14 (2006.01); G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—226 [365/201; 365/189.5; 365/154; 365/156] | 11 Claims |
| 1. A semiconductor memory device for storing information on a memory cell using a potential change in a word line and a bit
line, the semiconductor memory device comprising:
a memory cell having a circuit configuration in which a potential supplied to a source of a load transistor included in a
latch section is different from at least one of a potential supplied to the word line and a potential supplied to the bit
line;
a first control circuit for switching a normal operation mode and a test mode to each other in accordance with a signal applied
to a test mode setting pin; and
a second control circuit for controlling the potential supplied to the source of the load transistor to be lower than at least
one of the potential supplied to the word line and the potential supplied to the bit line, during an arbitrary period of at
least a read operation in the test mode,
wherein the second control circuit includes a plurality of transistors connected with each other in series between a power
supply and a ground potential,
the plurality of transistors includes at least a first transistor and a second transistor, and
a connecting point, at which the first transistor connects with the second transistor, connects with the source of the load
transistor.
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