| US 7,542,367 B2 | ||
| Semiconductor memory device | ||
| Kensuke Matsufuji, Fuchu (Japan); and Hiroshi Ito, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Aug. 15, 2007, as Appl. No. 11/839,199. | ||
| Claims priority of application No. 2006-226289 (JP), filed on Aug. 23, 2006. | ||
| Prior Publication US 2008/0049485 A1, Feb. 28, 2008 | ||
| Int. Cl. G11C 17/18 (2006.01) | ||
| U.S. Cl. 365—225.7 [365/96] | 11 Claims |
| 1. A semiconductor memory device, comprising:
a write voltage source capable of applying a write voltage;
an antifuse connected to said write voltage source and having one end supplied with said write voltage;
a first transistor having one end connected to the other end of said antifuse;
a first transistor controller configured to provide a first gate signal to the gate of said first transistor to controllably
turn on/off said first transistor;
a second transistor having one end connected to the other end of said first transistor and having the other end grounded;
a second transistor controller configured to provide a second gate signal to the gate of said second transistor to controllably
turn on/off said second transistor;
a sense node having one end connected to the other end of said first transistor;
a sense amp connected to said sense node and configured to compare the potential on said sense node with a reference potential;
and
a potential difference controller configured to accumulate charge on said sense node to control the potential difference placed
between both ends of said antifuse.
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