| US 7,542,361 B2 | ||
| Semiconductor integrated circuit device | ||
| Jumpei Sato, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 17, 2006, as Appl. No. 11/457,905. | ||
| Claims priority of application No. 2005-238230 (JP), filed on Aug. 19, 2005; and application No. 2006-149387 (JP), filed on May 30, 2006. | ||
| Prior Publication US 2007/0040599 A1, Feb. 22, 2007 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—205 [365/189.05; 365/189.08] | 20 Claims |
| 1. A semiconductor integrated circuit device comprising:
a boost circuit configured to boost power supply voltage so as to generate a boosted voltage;
a voltage detecting circuit configured to detect the boosted voltage of the boost circuit and control ON/OFF of the boost
circuit; and
a gate circuit configured to set the voltage detecting circuit to be in such an inactive state that current passage thereof
is shut off, or to be in such an active state that current passage thereof is conductive, wherein
the gate circuit generates a first activation signal for activating the voltage detecting circuit, and sets the voltage detecting
circuit to be in the inactive state while a load is separated from an output node of the boost circuit, wherein
the voltage detecting circuit comprises a first activation transistor disposed between the output node of the boost circuit
and ground potential node on the current passage, and wherein
the first activation transistor is turned on by the first activation signal provided to a gate thereof.
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