| US 7,542,360 B2 | ||
| Programmable bias for a memory array | ||
| Mahbub M. Rashed, Austin, Tex. (US); Robert E. Booth, Austin, Tex. (US); Sushama Davar, Austin, Tex. (US); and Giri Nallapati, Austin, Tex. (US) | ||
| Assigned to Freescale Semiconductor, Inc., Austin, Tex. (US) | ||
| Filed on Jul. 19, 2007, as Appl. No. 11/780,251. | ||
| Prior Publication US 2009/0021989 A1, Jan. 22, 2009 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—201 [365/185.25; 365/185.18; 365/189.09; 365/225.7] | 20 Claims |
| 1. A method for determining a body bias for a memory cell coupled to a bit line, comprising:
applying a first supply voltage to the memory cell and precharging the bit line to a voltage lower than the first supply voltage
as a first test condition representative of a first mode of operation of the memory cell;
providing a programmable bias voltage circuit that provides a bias voltage to the memory cell based on input values;
applying initial test values as the input values;
testing the memory cell with the memory cell in the first test condition using the initial test values to determine a pass
or a fail condition of the memory cell and retaining the initial values as the input values if the memory cell has a pass
condition; and
if the memory cell has a fail condition, testing the memory cell with the memory cell in the first test condition at changed
input values that are changed from the initial values, and if the changed input values result in the memory cell being in
a pass condition, configuring, in non-volatile fashion, the programmable bias voltage circuit to have the changed input values.
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