| US 7,542,357 B2 | ||
| Semiconductor device | ||
| Takeshi Sakata, Hino (Japan); Kenichi Osada, Tokyo (Japan); Riichiro Takemura, Tokyo (Japan); and Hideyuki Matsuoka, Nishitokyo (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Apr. 18, 2007, as Appl. No. 11/785,553. | ||
| Application 11/785553 is a continuation of application No. 11/359538, filed on Feb. 23, 2006, granted, now 7,224,599, filed on May 29, 2007. | ||
| Application 11/359538 is a continuation of application No. 10/754814, filed on Jan. 12, 2004, granted, now 7,038,961, filed on May 02, 2006. | ||
| Claims priority of application No. 2003-150080 (JP), filed on May 28, 2003. | ||
| Prior Publication US 2007/0195582 A1, Aug. 23, 2007 | ||
| Int. Cl. G11C 7/10 (2006.01) | ||
| U.S. Cl. 365—189.17 [365/148; 365/189.2; 365/185.33] | 3 Claims |
| 1. A memory card comprising:
a phase change memory cell array including a plurality of first word lines, a plurality of first bit lines intersected with
the plurality of first word lines, and a plurality of phase change memory cells arranged at respective positions where the
plurality of first word lines are intersected with the plurality of first bit lines;
a flash memory cell array including a plurality of second word lines, a plurality of second bit lines intersected with the
plurality of second word lines, and a plurality of non-volatile memory cells arranged at respective positions where the plurality
of second word lines are intersected with the plurality of second bit lines; and
a memory controller connected to the phase change memory cell array and the flash memory cell array,
wherein the memory controller controls the flash memory cell array and uses the phase change memory cell array as a buffer
memory cell array of the flash memory cell array.
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