| US 7,542,356 B2 | ||
| Semiconductor memory device and method for reducing cell activation during write operations | ||
| Kwang-Jin Lee, Hwaseong-si (Korea, Republic of); Sang-Beom Kang, Hwaseong-si (Korea, Republic of); Hyung-Rok Oh, Hwaseong-si (Korea, Republic of); Beak-Hyung Cho, Hwaseong-si (Korea, Republic of); and Woo-Yeong Cho, Suwon-si (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (Korea, Republic of) | ||
| Filed on Apr. 24, 2007, as Appl. No. 11/790,146. | ||
| Claims priority of application No. 10-2006-0107096 (KR), filed on Nov. 01, 2006. | ||
| Prior Publication US 2008/0101131 A1, May 01, 2008 | ||
| Int. Cl. G11C 7/06 (2006.01) | ||
| U.S. Cl. 365—189.07 [365/185.14; 365/189.16] | 18 Claims |
| 1. A method for writing data to a memory device comprising:
receiving N-bit write data;
reading N-bit cell data in the memory device;
reading a status bit in the memory device, the status bit being associated with the N-bit cell data;
if the status bit is high, inverting each bit of the N-bit cell data to produce inverted N-bit cell data and comparing each
bit of the inverted N-bit cell data with a corresponding bit of the N-bit write data to produce a first comparison data, and
if the status bit is low, comparing each bit of the N-bit cell data with a corresponding bit of the N-bit write data to produce
the first comparison data.
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