| US 7,542,349 B2 | ||
| Semiconductor memory device | ||
| Toshiki Rai, Gifu (Japan); and Sadao Yoshikawa, Gifu (Japan) | ||
| Assigned to SANYO Electric Co., Ltd., Osaka (Japan); and SANYO Semiconductor Co., Ltd., Gunma (Japan) | ||
| Filed on Nov. 28, 2007, as Appl. No. 11/946,674. | ||
| Claims priority of application No. 2006-323022 (JP), filed on Nov. 30, 2006. | ||
| Prior Publication US 2008/0130374 A1, Jun. 05, 2008 | ||
| Int. Cl. G11C 16/06 (2006.01) | ||
| U.S. Cl. 365—185.23 [365/185.22; 365/185.18; 365/185.05; 365/230.06; 365/242] | 4 Claims |
| 1. A semiconductor memory device comprising:
a plurality of nonvolatile memory cell transistors that are electrically data erasable and writable;
a source line connected to sources of the nonvolatile memory cell transistors;
a word line connected to control gates of the nonvolatile memory cell transistors;
a high voltage generation circuit generating a high voltage for erasing and writing data;
a high voltage switching circuit switching in response to a selection signal and outputting the high voltage generated by
the high voltage generation circuit;
a first switch outputting the high voltage outputted by the high voltage switching circuit to the source line in response
to a write enable signal;
a second switch outputting the high voltage outputted by the high voltage switching circuit to the word line in response to
an erase enable signal; and
a third switch outputting the high voltage generated by the high voltage generation circuit to the source line bypassing the
high voltage switching circuit in response to the write enable signal.
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