| US 7,542,347 B2 | ||
| Semiconductor device | ||
| Satoru Hanzawa, Hachioji (Japan); and Takeshi Sakata, Hino (Japan) | ||
| Assigned to Hitachi, Ltd., Tokyo (Japan) | ||
| Filed on Oct. 16, 2007, as Appl. No. 11/873,254. | ||
| Application 11/873254 is a continuation of application No. 11/409238, filed on Apr. 24, 2006, granted, now 7,286,430. | ||
| Application 11/409238 is a continuation of application No. 11/009449, filed on Dec. 13, 2004, granted, now 7,054,214. | ||
| Application 11/009449 is a continuation of application No. 10/726658, filed on Dec. 04, 2003, granted, now 6,862,232. | ||
| Application 10/726658 is a continuation of application No. 10/357222, filed on Feb. 04, 2003, granted, now 6,680,867. | ||
| Application 10/357222 is a continuation of application No. 09/933044, filed on Aug. 21, 2001, granted, now 6,563,743. | ||
| Claims priority of application No. 2000-364543 (JP), filed on Nov. 27, 2000. | ||
| Prior Publication US 2008/0089137 A1, Apr. 17, 2008 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.2 [365/189.02; 365/210] | 22 Claims |
| 1. A semiconductor device comprising:
a plurality of word lines;
a plurality of first memory cells being arranged at points of intersection of the plurality of word lines and a plurality
of first data lines and storing a first information or a second information;
a plurality of first dummy cells being arranged at points of intersection of the plurality of word lines and a first dummy
data line and storing the first information;
a plurality of second dummy cells being arranged at points of intersection of the plurality of word lines and a second dummy
data line and storing the second information;
a first multiplexer supplying a first potential to the plurality of first data lines;
a second multiplexer connected between the plurality of first data lines and a first writing circuit;
a third multiplexer supplying the first potential to the first dummy data line and the second dummy data line; and
a fourth multiplexer connected between the first dummy data line and the second dummy data line,
wherein a first writing circuit supplies the first potential to one of the plurality of the first data lines when the first
information is written in one of the plurality of first memory cells and supplies a second potential higher than the first
potential to one of the plurality of first data lines when the second information is written in one of the plurality of first
memory cells,
wherein the fourth multiplexer supplies the first potential to the first dummy data line and supplies the second potential
to the second dummy data line when the first information is written in the plurality of first dummy cells and the second information
is written in the plurality of second dummy cells.
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