| US 7,542,342 B2 | ||
| Multiple time programmable (MTP) PMOS floating gate-based non-volatile memory device for a general-purpose CMOS technology with thick gate oxide | ||
| Alexander Kalnitsky, San Francisco, Calif. (US); and Michael Church, Sebastian, Fla. (US) | ||
| Assigned to Intersil Americas Inc., Milpitas, Calif. (US) | ||
| Filed on Aug. 23, 2006, as Appl. No. 11/508,771. | ||
| Application 11/508771 is a continuation in part of application No. 11/498672, filed on Aug. 02, 2006, abandoned. | ||
| Claims priority of provisional application 60/793770, filed on Apr. 21, 2006. | ||
| Prior Publication US 2007/0121381 A1, May 31, 2007 | ||
| Int. Cl. G11C 16/04 (2006.01) | ||
| U.S. Cl. 365—185.1 [365/185.03] | 23 Claims |
| 1. A multiple time programmable (MTP) memory cell, comprising:
a floating gate PMOS transistor including a source that forms a first terminal of the memory cell, a drain and a gate;
a high voltage NMOS transistor including a source, an extended drain connected to the drain of the PMOS transistor, and a
gate forming a second terminal of the memory cell; and
an n-well capacitor including a first terminal connected to the gate of the PMOS transistor, and a second terminal forming
a third terminal of the memory cell;
wherein the floating gate PMOS transistor can store a logic state; and
wherein combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit
program, read and erase the logic state stored by the floating gate PMOS transistor.
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