| US 7,542,326 B2 | ||
| Semiconductor memory device | ||
| Satoshi Yoshimura, Kameyama (Japan); Shinichi Sato, Fukuyama (Japan); Satoru Yamagata, Fukuyama (Japan); and Shinji Horii, Tenri (Japan) | ||
| Assigned to Sharp Kabushiki Kaisha, Osaka (Japan) | ||
| Filed on Aug. 13, 2007, as Appl. No. 11/889,388. | ||
| Claims priority of application No. 2006-225811 (JP), filed on Aug. 22, 2006. | ||
| Prior Publication US 2008/0049487 A1, Feb. 28, 2008 | ||
| Int. Cl. G11C 11/00 (2006.01) | ||
| U.S. Cl. 365—148 [365/171; 365/173; 365/158] | 27 Claims |

| 1. A semiconductor memory device comprising:
an array of memory cells arranged in a row direction and a column direction, each memory cell including a series circuit of
a variable resistance element having two-port structure and an electrically openable and closable switch electrically connected
at one terminal to one port of the variable resistance element, each switch in the memory cells aligned along one row being
connected at a control terminal to a common word line extending in the row direction, one port other than the control terminal
of the memory cells aligned along one column being connected to a common bit line extending in the column direction, and the
other port other than the control terminal of the memory cell being connected to a source line extending in the row or column
direction; and
a voltage supplying means for conducting a first writing action for shifting an electrical resistance from a first state to
a second state by applying a first voltage between the bit line and the source line connected to a selected memory cell to
be written in the memory cell array and a third voltage to the word line connected to the control terminal of the switch in
the selected memory cell thus to apply a first write voltage between the two ports of the variable resistance element in the
selected memory cell, and for conducting a second writing action for shifting the electrical resistance from the second state
to the first state by applying a second voltage, which is opposite in the polarity to the first voltage, between the bit line
and the source line connected to the selected memory cell, and the third voltage to the word line connected to the control
terminal of the switch in the selected memory cell thus to apply a second write voltage between the two ports of the variable
resistance element in the selected memory cell, the second write voltage being opposite in the polarity to and different in
the absolute value from the first write voltage, wherein
the variable resistance element is a nonvolatile memory element capable of storing information so that the information can
be electrically written by shifting the electrical resistance between the first state and the second state when the first
write voltage and the second write voltage are applied to the two ports respectively,
the switch is an element that shifts conductivity from a conductive state to a non-conductive state or vice versa between
the first terminal and the second terminal according to a voltage applied to the control terminal, and
the voltage supplying means comprises an n-channel enhancement type MOSFET and a p-channel enhancement type MOSFET as drive
elements for driving the source line.
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