| US 7,542,325 B2 | ||
| Ferroelectric memory | ||
| Tadashi Miyakawa, Yokohama (Japan); and Daisaburo Takashima, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Minato-ku, Tokyo (Japan) | ||
| Filed on Oct. 17, 2007, as Appl. No. 11/873,764. | ||
| Claims priority of application No. 2006-282589 (JP), filed on Oct. 17, 2006. | ||
| Prior Publication US 2008/0089109 A1, Apr. 17, 2008 | ||
| Int. Cl. G11C 11/22 (2006.01); G11C 11/24 (2006.01) | ||
| U.S. Cl. 365—145 [365/149] | 16 Claims |
| 1. A ferroelectric memory, comprising:
a memory cell block of plural serially connected memory cells each including a cell transistor and a ferroelectric capacitor
connected in parallel therewith;
a cell transistor resistance measuring circuit configured to measure a resistance of the cell transistor;
a word line voltage controller configured to control a word line voltage applied to a gate of the cell transistor based on
the resistance of the cell transistor; and
a word line voltage generator configured to generate the word line voltage.
|