| US 7,542,323 B2 | ||
| Semiconductor memory device having a plurality of chips and capability of outputting a busy signal | ||
| Hiroshi Nakamura, Fujisawa (Japan); Kenichi Imamiya, Tokyo (Japan); and Ken Takeuchi, Stanford, Calif. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Sep. 24, 2004, as Appl. No. 10/949,274. | ||
| Application 10/949274 is a continuation of application No. 10/754993, filed on Jan. 08, 2004, granted, now 6,990,003. | ||
| Application 10/754993 is a continuation of application No. 10/185645, filed on Jun. 28, 2002, granted, now 6,680,858, filed on Jan. 20, 2004. | ||
| Claims priority of application No. 2001-198132 (JP), filed on Jun. 29, 2001; application No. 2001-377408 (JP), filed on Dec. 11, 2001; and application No. 2002-159518 (JP), filed on May 31, 2002. | ||
| Prior Publication US 2005/0036356 A1, Feb. 17, 2005 | ||
| Int. Cl. G11C 5/06 (2006.01) | ||
| U.S. Cl. 365—63 [365/189.05; 365/189.07; 365/191] | 13 Claims |
| 1. A semiconductor memory system comprising:
a first semiconductor memory device including a first circuit, and a second semiconductor memory device including a second
circuit,
the second circuit detects a first busy state of the first semiconductor memory device, and the first circuit detects a second
busy state of the second semiconductor memory device.
|