| US 7,542,321 B2 | ||
| Semiconductor memory device with power supply wiring on the most upper layer | ||
| Hiroshi Maejima, Milpitas, Calif. (US); Takumi Abe, Mountain View, Calif. (US); and Makoto Hamada, Mountain View, Calif. (US) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Jul. 24, 2007, as Appl. No. 11/782,311. | ||
| Prior Publication US 2009/0027941 A1, Jan. 29, 2009 | ||
| Int. Cl. G11C 5/02 (2006.01) | ||
| U.S. Cl. 365—51 [365/63] | 20 Claims |
| 1. A semiconductor memory device comprising:
a semiconductor substrate;
a memory cell array in the semiconductor substrate, the memory cell array having a plurality of memory cells arranged in rows
and columns;
a first circuit located at one end of the memory cell array in a column direction;
a second circuit located at the other end of the memory cell array in the column direction; and
a first wire located above the memory cell array between the first circuit and the second circuit, the first wire being located
in a most upper layer in the semiconductor substrate to supply power to the second circuit.
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