| US 7,542,018 B2 | ||
| Light emitting device and drive method thereof | ||
| Aya Anzai, Tsukui Kanagawa (Japan); Mitsuaki Osame, Kanagawa (Japan); Yoshifumi Tanada, Kanagawa (Japan); Keisuke Miyagawa, Kanagawa (Japan); Satoshi Seo, Kanagawa (Japan); and Shunpei Yamazaki, Tokyo (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., (Japan) | ||
| Filed on Sep. 26, 2007, as Appl. No. 11/861,494. | ||
| Application 11/321992 is a division of application No. 11/147527, filed on Jun. 08, 2005. | ||
| Application 11/861494 is a continuation of application No. 11/321992, filed on Dec. 29, 2005, granted, now 7,276,856. | ||
| Application 11/147527 is a continuation of application No. 10/376366, filed on Feb. 27, 2003, granted, now 7,023,141, filed on Apr. 04, 2006. | ||
| Claims priority of application No. 2002-055840 (JP), filed on Mar. 01, 2002. | ||
| Prior Publication US 2008/0036709 A1, Feb. 14, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G09G 3/30 (2006.01) | ||
| U.S. Cl. 345—76 [345/80; 345/92; 345/204; 345/214] | 13 Claims |
| 1. A light emitting device comprising:
a source signal line provided over a substrate;
a gate signal line for writing provided over said substrate;
a gate signal line for blanking provided over said substrate;
an electric current supplying line provided over said substrate;
a switching transistor provided in a pixel and over said substrate;
a driving transistor provided in said pixel and over said substrate;
a blanking transistor provided in said pixel and over said substrate;
a pixel electrode provided in said pixel and over said substrate and connected with one of a source region and a drain region
of said driving transistor;
a counter electrode provided over said substrate;
an electroluminescence element provided in said pixel and comprising a light emitting layer, said light emitting layer provided
over said substrate and between said pixel electrode and said counter electrode; and
a switch connected with said counter electrode for switching a potential of said counter electrode from one of a first potential
and a second potential to the other,
wherein one of a source region and a drain region of said switching transistor is connected with said source signal line,
and the other of said source region and said drain region of said switching transistor is connected with a gate electrode
of said driving transistor, and a gate electrode of said switching transistor is connected with said gate signal line for
writing,
wherein one of a source region and a drain region of said driving transistor is connected with said electric current supplying
line, and the other of said source region and said drain region of said driving transistor is connected with said pixel electrode,
wherein a gate electrode of said blanking transistor is connected with said gate signal line for blanking, and one of a source
region and a drain region of said blanking transistor is connected with said electric current supplying line, and the other
of said source region and said drain region of said blanking transistor is connected with said gate electrode of said driving
transistor,
wherein said first potential is applied to said counter electrode to apply a forward bias voltage between said pixel electrode
and said counter electrode, and said second potential is applied to said counter electrode to apply a reverse bias voltage
between said pixel electrode and said counter electrode, and
wherein said reverse bias voltage has polarity inversed with respect to said forward bias voltage.
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