| US 7,541,862 B2 | ||
| Reference voltage generating circuit | ||
| Hiroki Fujisawa, Tokyo (Japan); Masayuki Nakamura, Tokyo (Japan); and Hitoshi Tanaka, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Nov. 22, 2006, as Appl. No. 11/603,121. | ||
| Claims priority of application No. 2005-354872 (JP), filed on Dec. 08, 2005. | ||
| Prior Publication US 2007/0132506 A1, Jun. 14, 2007 | ||
| Int. Cl. G05F 1/10 (2006.01); G05F 3/02 (2006.01) | ||
| U.S. Cl. 327—539 [327/513; 327/540; 327/542; 323/313; 323/316] | 8 Claims |
| 1. A reference voltage generating circuit comprising:
a current generating section that generates a first current having a positive temperature coefficient;
a voltage generating section that generates a voltage having a negative temperature coefficient;
a synthesis section that generates a voltage which is the sum of a voltage having a positive temperature coefficient and developed
across both terminals of a resistor by causing a current having a positive temperature coefficient to flow through said resistor,
and said voltage having a negative temperature coefficient; and
a compensation current generating section that generates a second current having a positive temperature coefficient;
a current corresponding to the sum of said first and second currents being caused to flow through said resistor;
said synthesis section generating a voltage which is a sum of a terminal voltage of said resistor by the sum current of said
first and second currents and said voltage having a negative temperature coefficient; said synthesis section outputting the
voltage generated as a reference voltage,
wherein said compensation current generating section outputs, as said second current, a current proportional to a differential
voltage corresponding to subtraction of said voltage having the negative temperature coefficient from said reference voltage
output from said synthesis section.
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