| US 7,541,860 B2 | ||
| Current control circuit used for voltage booster circuit | ||
| Eiji Yasuda, Osaka (Japan); and Tadayoshi Nakatsuka, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Mar. 06, 2008, as Appl. No. 12/43,310. | ||
| Claims priority of application No. 2007-059469 (JP), filed on Mar. 09, 2007. | ||
| Prior Publication US 2008/0218240 A1, Sep. 11, 2008 | ||
| Int. Cl. G05F 3/00 (2006.01) | ||
| U.S. Cl. 327—536 [326/87; 363/60] | 10 Claims |
| 1. A current control circuit which is used for a voltage booster circuit and which has a direct coupled FET logic circuit
configured with a depletion-mode FET or with an enhancement-mode FET, the current control circuit comprising:
a logic circuit including a transistor section, which outputs one of a high level voltage and a low level voltage to a drain
of the transistor section in accordance with a logic signal inputted to a gate of the transistor section, and including a
load, where one end of the load is connected to the drain of the transistor section;
a first switch circuit, which is placed between the other end of the load and a power supply end of the voltage booster circuit,
and which enters a conduction state when the high level voltage is outputted to the drain of the transistor section; and
a second switch circuit which is placed between the other end of the load and an external power supply, and which enters the
conduction state when the low level voltage is outputted to the drain of the transistor section.
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