a substrate having a surface and a substrate pad thereon;

a memory chip stacked on the substrate and having a memory chip pad connected to a common pin receiving a common memory chip signal;

an interposer chip stacked between the substrate and the memory chip having an interposer pad connected to the memory chip pad; and

a secondary chip stacked between the substrate and the interposer chip and having

a common pin;

a bypass circuit having switching circuits;

a first analog logic pin connected between the substrate pad and the bypass circuit; and

a second analog-logic pin connected between the bypass circuit and the interposer pad,

wherein during a direct access test of the secondary chip, the switching circuits of the bypass circuit are configured to disconnect the first analog-logic pin from the second analog-logic pin, and connect the first analog-logic pin to the common pin; and

during a direct access test of the memory chip, the switching circuit of the bypass circuit are configured to disconnect the common pin from the first analog-logic pin and connect the first and second analog-logic pins.