US 7,541,661 B2
Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs
Hideki Yasuoka, Musashino (Japan); Masami Kouketsu, Hachioji (Japan); Susumu Ishida, Tachikawa (Japan); and Kazunari Saitou, Mobara (Japan)
Assigned to Renesas Technology Corp., Tokyo (Japan)
Filed on Dec. 21, 2006, as Appl. No. 11/614,469.
Application 11/614469 is a division of application No. 10/894019, filed on Jul. 20, 2004, granted, now 7,224,037, filed on May 29, 2007.
Application 10/894019 is a continuation of application No. 10/327859, filed on Dec. 26, 2002, abandoned.
Application 10/327859 is a continuation of application No. 09/989061, filed on Nov. 21, 2001, granted, now 6,780,717, filed on Aug. 24, 2004.
Claims priority of application No. 2000-364146 (JP), filed on Nov. 30, 2000.
Prior Publication US 2007/0096247 A1, May 03, 2007
Int. Cl. H01L 27/092 (2006.01)
U.S. Cl. 257—501  [257/389; 257/E27.064] 23 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit device having a display driver, comprising:
a gate insulating film of a first MISFET formed over a semiconductor substrate;
a gate electrode of said first MISFET formed over said gate insulating film;
first semiconductor regions formed in said semiconductor substrate, wherein said first semiconductor regions serve as part of source and drain regions of said first MISFET;
an insulating film formed in said semiconductor substrate, said insulating film being arranged between said first semiconductor regions and a semiconductor region under said gate insulating film,
second semiconductor regions formed in said semiconductor substrate and surrounding first semiconductor regions and said insulating film, wherein said second semiconductor regions serve as part of source and drain regions of said first MISFET,
wherein an impurity concentration of said first semiconductor regions is higher than an impurity concentration of said second semiconductor regions,
wherein said insulating film is thicker than said gate insulating film,
wherein ends of said gate electrode are formed over said insulating film in a direction from said source region to said drain region,
wherein said insulating film is embedded in a groove of said semiconductor substrate, and
wherein ends of said gate insulating film are formed over said insulating film in said source/drain direction.