first and second blocks in which a plurality of cell units having a plurality of memory cells connected in series and selection gate transistors connected with both ends of each of the plurality of memory cells are arranged;

a shunt region which is arranged between the first block and the second block and in which the memory cell is not formed, and which contains a first activation region formed in the shunt region to extend in a first direction;

a first selection gate line as a first control gate of the selection gate transistor which is formed to extend in the first and second blocks and in the shunt region in a second direction perpendicular to the first direction, the first selection gate line having a first gate electrode, a first inter-gate insulating film formed on the first gate electrode and a second gate electrode formed on the first inter-gate insulating film, the first inter-gate insulating film having a first opening portion contacting the first gate electrode with the second gate electrode;

a second selection gate line formed above the first selection gate line; and

a first contact material which is formed on the first selection gate line in the shunt region and electrically connects the first selection gate line and the second selection gate line with each other,

wherein:

the shunt region contains an intersection region at which the first activation region and the first selection gate line intersect each other;

the intersection region is provided without containing the first opening portion, and in the intersection region, the first inter-gate insulating film isolates the first gate electrode and the second gate electrode in the first selection gate line from each other; and

in the intersection region, the first contact material is located on a line which extends from the first opening portion in the first selection gate line in a longitudinal direction of the first opening portion.