| US 7,541,646 B2 | ||
| Thin film transistor device and method of manufacturing the same | ||
| Hitoshi Nagata, Tokyo (Japan); Takao Sakamoto, Tokyo (Japan); and Naoki Nakagawa, Tokyo (Japan) | ||
| Assigned to Mitsubishi Electric Corporation, Tokyo (Japan) | ||
| Filed on Feb. 12, 2007, as Appl. No. 11/673,773. | ||
| Claims priority of application No. 2006-063368 (JP), filed on Mar. 08, 2006. | ||
| Prior Publication US 2007/0210353 A1, Sep. 13, 2007 | ||
| Int. Cl. H01L 21/84 (2006.01) | ||
| U.S. Cl. 257—347 [257/E21.561; 257/759; 257/760] | 7 Claims |
| 1. A thin film transistor device, comprising:
a thin film transistor having a silicon layer including a source region, a drain region, and a channel region, a gate insulating
layer, and a gate electrode formed on an insulating substrate;
an interlayer insulating layer covering the thin film transistor;
a line electrically connected with the source region, the drain region, and the gate electrode through a contact hole formed
in the interlayer insulating layer;
a first upper insulating layer covering the line and the interlayer insulating layer directly and smoothing out stepped portions
of the line and irregularities of a surface of the interlayer insulating layer; and
a second upper insulating layer covering the first upper insulating layer,
the second upper insulating layer having a hydrogen diffusion coefficient smaller than a hydrogen diffusion coefficient of
the first upper insulating layer;
wherein the first upper insulating layer is a single layer comprising one of an organic Spin On Dielectrics (SOD) film, an
organic Spin On Glass (SOG) film, an inorganic SOD film, an inorganic SOG film, and a high-heat-resistance organic polymer
film resistant to a temperature of about 400° C. or higher.
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