| US 7,541,645 B2 | ||
| Metal oxide semiconductor (MOS) transistors having buffer regions below source and drain regions | ||
| Sung-Min Kim, Incheon-si (Korea, Republic of); Dong-Gun Park, Gyeonggi-do (Korea, Republic of); Sung-Young Lee, Gyeonggi-do (Korea, Republic of); Hye-Jin Cho, Gyeonggi-do (Korea, Republic of); Eun-Jung Yun, Seoul (Korea, Republic of); Shin-Ae Lee, Gyeonggi-do (Korea, Republic of); Chang-Woo Oh, Gyeonggi-do (Korea, Republic of); and Jeong-Dong Choe, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of) | ||
| Filed on Aug. 31, 2006, as Appl. No. 11/513,474. | ||
| Application 11/513474 is a division of application No. 10/754676, filed on Jan. 09, 2004, granted, now 7,122,431. | ||
| Claims priority of application No. 10-2003-02995 (KR), filed on Jan. 16, 2003; and application No. 10-2003-79861 (KR), filed on Nov. 12, 2003. | ||
| Prior Publication US 2006/0289907 A1, Dec. 28, 2006 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—347 [257/396; 257/401; 257/288; 257/E29.021; 257/E29.275; 257/E29.298; 438/197] | 9 Claims |
| 1. A semiconductor device, comprising:
an epitaxial layer on the substrate, the epitaxial layer being defined by device isolation layers;
a gate on the epitaxial layer;
a source region and a drain region in the epitaxial layer outside the gate, the epitaxial layer between the source region
and the drain region constituting a channel region; and
first and second spaced apart buffer regions beneath the source region and the drain region, respectively, and between respective
ones of the source region and the substrate and the drain region and the substrate, wherein the buffer regions are confined
between the device isolation layers,
wherein a bottom surface of the gate is lower than bottom surfaces of the first and second buffer regions and wherein a bottom
surface of the channel region is lower than the bottom surface of the first and second buffer regions.
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