| US 7,541,642 B2 | ||
| Semiconductor device with a gate electrode including a pair of polysilicon layers | ||
| Keiko Kawamura, Yokohama (Japan); and Masanobu Tsuchitani, Kawasaki (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Oct. 07, 2005, as Appl. No. 11/245,042. | ||
| Claims priority of application No. 2005-215671 (JP), filed on Jul. 26, 2005. | ||
| Prior Publication US 2007/0023828 A1, Feb. 01, 2007 | ||
| Int. Cl. H01L 29/78 (2006.01) | ||
| U.S. Cl. 257—331 [257/330; 257/332; 257/333; 257/334; 257/E29.201] | 9 Claims |
| 1. A semiconductor device having a trench gate, comprising:
a semiconductor substrate having a gate trench formed therein;
a gate insulator formed along sides and the bottom of said gate trench in said semiconductor substrate; and
a gate electrode formed on said gate insulator in said gate trench, said gate electrode including a pair of polysilicon layers
formed along sides of said gate trench, with a gate metal layer buried in between sides of upper portions of said pair of
said polysilicon layers and extending along said gate trench
an intermediate insulator buried in between portions of said pair of said polysilicon layers except said upper portions;
a source contact metal layer connected to a contact surface of the semiconductor substrate, said source contact metal layer
having an upper surface coplanar with that of the gate metal layer;
a metal isolation layer formed to isolate said gate metal layer from said source contact metal layer and having an upper surface
formed coplanar with upper surfaces of both said metal layers;
an interlayer insulator covering an upper end of said gate electrode; and
a first main electrode covering said interlayer insulator and connected to said source contact metal layer.
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